LEAD SYSTEM ENGINEER – PLATFORM & HARDWARE

LEAD SYSTEM ENGINEER – PLATFORM & HARDWARE

LEAD SYSTEM ENGINEER – PLATFORM & HARDWARE BANGALORE •  INDIA   About Airspan Networks Airspan Networks is a leading provider of groundbreaking wireless solutions, enabling connectivity for the next generation of mobile and fixed networks. With a global presence, Airspan focuses on delivering innovative technologies that drive advancements in Open RAN and accelerate 5G adoption worldwide. Backed by strong investments and a team of world-class experts, Airspan supports telecom operators and enterprises in achieving their digital transformation goals. At Airspan, we’re on the cutting edge of 4G and 5G RAN software and hardware development, creating innovative solutions that drive the future of wireless connectivity. With over a million cells deployed worldwide, our disruptive Open RAN platform is transforming carrier networks and critical infrastructure across the globe. Airspan is more than just a workplace; it’s a launchpad for your career. We are dedicated to pushing the boundaries of technology and innovation, ensuring a bright future for both our company and our employees. Our greatest strength lies in our people—a team of brilliant minds from diverse backgrounds working together to achieve extraordinary results. With offices in the USA, UK, India, Colombia, Poland, Japan, and Israel, Airspan offers a global working environment that values collaboration, creativity, and excellence. Whether you’re based in one of our offices or working remotely, you’ll be part of a dynamic team shaping the future of connectivity.   About the Role: We are seeking a highly capable and experienced Platform and Hardware Lead System Engineer with a strong background in eNB/gNB Hardware and Platform System Design, O-RAN hardware architecture, and SoC-based radio platforms. The ideal candidate will lead hardware platform definition and integration efforts, ensuring end-to-end performance, energy efficiency, and ODM Interfacing in 4G/5G systems. The role demands hands-on experience with O-RAN hardware specifications, RF components, and system profiling for Board Design. The candidate will actively interface with ODM partners to define, negotiate, and validate hardware platforms that meet carrier-grade expectations and acceptance. The candidate shall be able to profile hardware resource needs based on application requirements, select appropriate controllers or server boards per compute and thermal budget, and translate system-level constraints into detailed hardware requirements for development and vendor interaction.   Job description: Deep expertise in eNB and gNB platform and hardware design, including bring-up initialization Sequence. Strong understanding of RU hardware design, eCPRI, PHY Split architectures (e.g., Split 7.2x), and SU/MU-MIMO systems. Hands-on experience with O-RAN Indoor Small Cell and Outdoor Micro Cell Hardware   Key Responsibilities: Architecture and Requirements, and exposure to O-RAN Network Energy Saving metrics and procedures. Proven experience with FSM10055 mmWave and FSM10056 Sub-6 GHz SoCs, including SDR RFIC and PHY integration. Design experience in SDR RFIC, DFE, and RFFE integration over COMe-based carrier boards. Familiarity with mezzanine based modular board system designs.ss Ability to deep dive ORAN HW reference designs. Ability to deep dive SoC (Qualcomm, Intel , EdgeQ) reference designs. Solid understanding of PMIC module for power profiling. Design knowledge of power reset circuits. Strong command over FPGA-based platforms and SoC integration, with practical use of MATLAB, VHDL for simulation and validation. Experience with Cadence Allegro for PCB schematic capture, layout review, and design verification. Skilled in resource profiling for system functions (e.g., baseband processing, RF chains, digital interfaces) and hardware controller/server board selection based on project-specific compute and IO demands. Ability to interface directly with ODM partners, articulate hardware requirements, define acceptance criteria, and ensure conformance to specifications. Knowledge of ATE-stage validation procedures, including calibration, PA/LNA linearization, and system-level MTBF and thermal analysis. Working knowledge of Dual Doherty PA. Hands-on involvement in SDR9000 RFIC, and validation of RFFE interfaces. Experience with QDART. Working knowledge hardware interfaces and IO expanders: SPI, UART, I2C. Proficiency in preparing Visio-based hardware block diagrams and managing hardware reference design documents. Ability to compile and manage Bill of Materials (BOM) accurately for system-level hardware builds. Familiarity with clock units, hard sync techniques, PTP, SyncE, and GPS modules for synchronization and timing architecture. Exposure to EDA tools (e.g., Synopsys, Cadence) Internship or thesis projects in semiconductor labs or companies Research publications in IEEE on digital/SoC/FPGA topics   Required Qualification: Master / PhD in Electronics and Communication Engineering, Digital Design, Embedded Systems Design or a related field. 15–20 years of experience in Wireless Embedded Platform Designs, with a strong foundation in LTE and 5G NR technologies with ORAN and 3GPP Knowledge.   Required Qualification: Good level of English Service Oriented Excellent communication and interpersonal skills Problem solver, proactive and efficient Self-learning capabilities   Why Join Us?: At Airspan, you’ll work in an environment that values flexibility and innovation. Whether you’re an experienced professional or looking to grow your career, you’ll be joining a team that prioritizes collaboration and creativity. Be part of a company with a global reach, a strong track record, and an exciting vision for the future of wireless connectivity.   Apply today and help us drive the future of telecommunications!